Managing the Multi-Gbit/s Test Challenges

CMOS technology continues to evolve following Moore’s law enabling new levels of integration, performance and cost. Within a fairly short period of time we will see a pretty significant architectural transformation within desktop computers, servers, laptops, and even in your digital entertainment center: The multi-drop buses transform into an on-board packet switched network connecting high-performance chips with differential high-speed point-to-point links. Serial ATA is leading the pack, PCI-Express is emerging, just to name a few, they will soon be common-place to the PC industry. Chipsets in the computation and consumer space are under severe cost pressure, which creates a severe challenge to the traditional test strategies. Structural test methodologies and associated development tools have emerged and provide a notion of: As soon as everything is synthesized digitally, there is no need for big iron ATE anymore. So while the ATE industry is squeezing to provide ever more economic solutions there is a raising concern as to how to ECONOMICALLY MANUFACTURE gigabit links without biting into $ margins.